MeOoOw Processor

Design and implement a superscalar Out-of-Order (OoO) RISC processor featuring explicit register renaming, dynamic scheduling, and reorder buffer (ROB) for high IPC and efficient instruction-level parallelism.

Verified individual components through directed tests and constrained-random verification in SystemVerilog, leveraging the Synopsys toolchain for simulation, synthesis, waveform analysis, and timing closure.